REV. A
ADM1027
51
Table XXIV. XOR Tree Test Enable
Register Address
R/W
Description
Power-On Default
0x6F
Read/Write
XOR Tree Test Enable Register
0x00
<0>
XEN
If the XEN bit is set to 1, the device enters the XOR tree test mode. Clearing the bit
removes the device from the XOR tree test mode.
<7:1>
Reserved
Unused. Do not write to these bits.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Table XXV. Remote 1 Temperature Offset
Register Address
R/W
Description
Power-On Default
0x70
Read/Write
Remote 1 Temperature Offset
0x00
<7:0>
Read/Write
Allows a twos complement offset value to be automatically added to or subtracted from
the Remote 1 temperature reading. This is to compensate for any inherent system offsets
such as PCB trace resistance. LSB value = 1
o
C.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Table XXVI. Local Temperature Offset
Register Address
R/W
Description
Power-On Default
0x71
Read/Write
Local Temperature Offset
0x00
<7:0>
Read/Write
Allows a twos complement offset value to be automatically added to or subtracted from
the local temperature reading. LSB value = 1
o
C.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
Table XXVII. Remote 2 Temperature Offset
Register Address
R/W
Description
Power-On Default
0x72
Read/Write
Remote 2 Temperature Offset
0x00
<7:0>
Read/Write
Allows a twos complement offset value to be automatically added to or subtracted from
the Remote 2 temperature reading. This is to compensate for any inherent system off-
sets such as PCB trace resistance. LSB value = 1
o
C.
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register
will have no effect.
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